1. Field of the Invention
This invention relates to wafer testing of integrated circuits, and more particularly for methods to test complex LSI chips having both controller logic and memory.
2. Description of the Related Art
Rapid advances in semiconductor process technology has resulted in a marked increase in the density of functions that may be integrated onto a chip. LSI chips may include large logic blocks containing thousands of gates. Large memories may also be combined on the same silicon die with the logic blocks. One particular LSI application is for a graphics memory controller chip. The graphics or video controller contains several large, complex logic blocks to manipulate and control pixel data which forms the video image to be displayed on a screen. A large video memory of one-half to several megabytes is controlled by this video controller. This size is larger by several orders of magnitude than static-RAM cache memories commonly used on microprocessor chips. Video memories must use dynamic RAM (DRAM) to achieve the mega-byte memory size while cache memories can use faster SRAM since only a few K-bytes are needed.
While smaller cache memories can be tested on a standard logic test machine simply by writing test vectors to test each SRAM memory cell, the large size of the video DRAM memory requires a huge number of test vectors. Special testers have been developed for testing large memories such as DRAMs. These memory testers can generate the test vectors in real time from a test program. For example, the test program may be written in a higher-level programming language. The test program includes statements in a loop construct that are repeated thousands of times. These statements generate a test vector each time the loop is iterated. In contrast, a logic tester simply contains a storage area containing the test vectors themselves which are sequentially retrieved from the logic tester's storage area and sent to the device under test. The logic test `program` therefore does not have to be written in a higher-level programming language but merely causes previously-written test vectors to be retrieved from storage and sent to the pins of the device or IC being tested.
A problem occurs when a large memory such as a DRAM is integrated onto the same silicon chip as a large logic controller. Since the logic tends to be random, a logic tester is needed to store vectors of test stimuli and expected outputs to test the random logic. These test patterns must be stored because there is no apparent pattern or sequence to the test vectors and thus they cannot be generated on the fly using logical statements in a test program. However, this storage is not large enough to test a large memory, since several million test vectors are needed to test a megabyte memory. A memory tester should be used since the memory tester can generate the test vectors from logical statements in a test program which describe a pattern or sequence. Common memory test patterns that can easily be described by such logical statements in a test pattern include up or down counter test patterns or checkerboard or walking ones or zeros patterns. Any hybrid tester which can perform both logic and memory tests would be too expensive and not cost-effective.
Thus each die or chip must be tested with two different tester machines--the controller logic is tested with a logic tester, while the large DRAM memory is tested with a memory tester. It is common to repair a memory by using a laser repair station which can blow `fuses` on the die to enable redundant or spare memory cells to replace defective memory cells. The memory test must be repeated after repair to determine if the repair was successful.
The high cost of integrated circuit packages dictates that the logic and memory tests and laser repair be performed before the wafer is cut and the die are packaged. Wafer sort machines are used to successively connect the logic or memory tester with the die on the wafer. FIG. 1 shows that a silicon wafer is composed of many separate die 10. Each die 10 is separated from other die 10 by a scribe area 12. Each die 10 includes bonding pads 30. FIG. 2 is a cross-sectional view of a wafer-sort probe card above a wafer. The wafer sorter has a probe card 14 with small needle pins or probes 20 that are lowered to make contact with metal bonding pads 30 on the die 10 on the wafer.
While most probes 20 have tips that lie in a plane, occasionally one or more probes 20A is mis-aligned and has its tip below the other probe tips. Probe 20A makes contact with bonding pad 30A before the other probes 20. Indeed, for other probes 20 to make contact with bonding pads 30, additional pressure must be exerted on probe 20A after its has made contact with bonding pad 30A. This additional pressure or force can cause probe 20A to gouge out a portion of bonding pad 30A. Thus while aligned probes 20 make contact with bonding pads 30 as they touch the surface of pads 30, mis-aligned probe 20A has additional force placed upon it, gouging into pad 30A.
In a manufacturing production environment, it is not possible to have all probes perfectly aligned at all times. In addition, to ensure a firm electrical contact between probes 20 and bonding pads 30, an additional force is often applied. Thus even aligned probes 20 may leave gouge marks on pads 30, although the gouging from mis-aligned probe 20A is most severe.